1. Field of the Invention
The present invention relates generally to electronic packaging of semiconductor integrated circuits, and particularly, to electronic packaging of photo-sensing semiconductor devices. More specifically, the present invention relates to electronic packaging of photo image sensors in such compact applications as cellular telephone camera modules.
2. Prior Art
FIGS. 1A, 1B illustrate top and bottom views of typical camera modules 1, 3 often employed in cellular telephones. In the smaller of the modules 3, the lens housing is removed to more clearly show the module's internal configuration. A photo-sensor 3a is provided at each module's center, and a plurality of decoupling capacitors 3b are disposed thereabout.
A popular technique employed in the fabrication of such cellular phone camera modules is currently the so-called chip-on-board (COB) technique by which a module structure illustrated in the schematic cross-sectional view of FIG. 2 is realized. For clarity, extraneous devices like decoupling capacitors are omitted from the illustrated view. As shown, the COB-formed module includes a photo-image sensor 5; a printed circuit board (PCB) 7 to which the photo-image sensor 5 is attached using epoxy; and, gold-wire conductors for interconnections between the photo-image sensor 5 and the PCB 7. The module also includes in typical applications a plurality of passive devices such as the decoupling capacitors, connected to the PCB, which are not shown in the Figure to preserve clarity. The module further includes a molded housing (or barrel) 11 that extends over the assembled PCB 7. Within this housing 7 are positioned appropriate optical lenses 13 and an infrared (IR) cut filter glass member 15.
Attached to the PCB is a flexible film member 17 in which electrical interconnection lines are run. This flexible film member 17 allows for various camera module positions and orientations without breakage of electrical connections. As shown, one end of this flexible film member 17 makes electrical connections with the PCB 7 to which it is attached, and the other end extends therefrom for connection to a controller through, for example, a connector 19. Typically, four different metal layers are employed in a PCB 7 to effect the necessary electrical interconnections. One or two separate metal layers are typically employed in a flexible film member 17, one layer for signal lines and, if necessary, an additional layer for a ground plane underneath.
One reason for the COB technique's popularity in camera module applications is its compact size. Compact size is a most important requirement in such hand-held applications. In other applications where compact size is not as important a consideration, packaged photo-image sensors are generally preferred, as they offer better protection for the photo-sensor, and are easier to assemble on a PCB using a well known surface mounting technology (SMT). Packaged photo-image sensor types include ceramic leadless chip carrier (CLCC), an epoxy laminate version of the CLCC (in which the ceramic substrate is replaced by a less expensive epoxy laminate substrate much like that used in plastic ball grid array (PBGA) packages), and plastic leadless chip carrier (PLCC)—another less expensive variation of the CLCC. Unfortunately, none of these packaged photo-sensor image types are, in practice, viable alternatives for cellular phone camera module applications because of the resulting module's excessive size.
FIG. 3 shows a schematic cross-sectional view of a typical CLCC photo-sensing device. As shown in the figure, a photo-sensing semiconductor die is mounted face-up on a ceramic substrate 4 by using epoxy or the like inside of an enclosure that is covered by a glass lid 6. Wire bonding 8 is typically used to connect the photo-sensing die 2 to the ceramic substrate 4. Solderable pads 10 are provided on the bottom of ceramic substrate 4 to connect the package to a circuit board.
Other techniques are known for those applications where even more compact size than is realizable with the COB technique is sought. One such other technique is a chip scale (or size) package (CSP) technique. This CSP technique yields a packaged device whose overall package size is comparable (equal to or slightly greater than) typical chip sizes, so that the resulting module's size after full assembly is comparable to, or even less than, that of a COB module.
A known CSP packaging approach for photo-sensing semiconductor devices is one offered by Shellcase, Inc. Detailed techniques are disclosed by U.S. Pat. Nos. 5,716,759, 6,040,235, and 6,117,707. FIG. 4 shows a schematic cross-section of a package formed in accordance with those techniques, wherein a patterned metal layer is applied to a photo-sensing semiconductor wafer to extend bonding pads to its dicing area having a narrow width between neighboring dice. A photo-sensing wafer is attached to a glass substrate by using epoxy. After that, the backside of the wafer is ground to thin out the wafer. The silicon of the dicing area is then removed to expose metal lines. Many more process steps are needed to complete fabrication, but a detailed explanation is omitted, as such is not necessary for a clear understanding in the present invention.
The advantage of this package compared to a CLCC package is its smaller size. A number of drawbacks are nonetheless found in this package as well. Perhaps the most critical drawback with this package is the complexity both in structure and fabrication process. This complexity is a significant factor in mass production since complexity tends to increase the processing yield loss. As a result of its complexity and attendant yield loss, the package is expensive to fabricate.
Other nontrivial disadvantages of this technique include its need for a wide dicing line, which cuts against the trend in semiconductor manufacturing to decrease the width of dicing lines to achieve more dice per wafer. The current typical dicing line width of about 100 micrometers is not wide enough to support this technique. Consequently, the packaging technique is not compatible with semiconductor wafers having standard dicing line widths, and requires customizing measures to ensure the wider than usual dicing line widths.
FIG. 5 illustrates a schematic cross-sectional view in one embodiment of the electronic package disclosed in co-pending Parent application Ser. No. 10/692,816. The electronic package 401 is shown assembled onto a printed circuit board (PCB) 402. The package 401 includes a transparent substrate 404 which extends over a photo-image sensor die 406 (disposed as shown as facing the substrate 404). Light L then reaches the photo-image sensor die 406 through the substrate 404.
A set of solder joints 408 are used between the photo-image sensor die 406 and substrate 404 to form electrical interconnections. A larger set of solder joints 420 are used outside and about the photo-image sensor die 406 to make electrical interconnections between the electronic package 401 and the PCB 402.
This unique electronic packaging approach offers numerous advantages over other packaging techniques. The resulting package size may be minimized even further, however, by reducing in size, and/or altogether removing at least some of the larger solder joints 420.
Accordingly, it is an object of the present invention to provide a highly minimized package size for photo-sensing devices to accommodate hand-held applications like cellular phone cameras. Another object of the present invention is to provide a lower cost package for photo-sensing devices.